1. Field
The present invention relates to an insulating sheet and a method of manufacturing the insulating sheet, and to a printed circuit board using the insulating sheet and a method of manufacturing the printed circuit board.
2. Description of the Related Art
Current electronic devices are trending towards smaller, thinner, and lighter products. In step with these trends, the preferred methods for mounting semiconductor chips are changing from wire bonding methods to flip chip methods, which allow greater numbers of terminals. Furthermore, there is a demand also for higher reliability and higher densities in the multi-layer printed circuit board, to which semiconductor chips may be mounted.
In the conventional multi-layer printed circuit board, when glass fiber woven fabric is used for the base material, E-glass fiber, etc., is generally used for the glass fiber component.
A thermosetting resin composition may be impregnated into the glass fiber woven fabric and dried, to produce a B-stage insulation sheet, which can then be processed into a copper clad laminate. This copper clad laminate can be used to fabricate a printed circuit board core, for use in the inner layers, after which B-stage insulation sheets may be arranged and stacked on either side as build-up layers, to manufacture a multi-layer printed circuit board.
In a multi-layer printed circuit board such as that described above, a build-up resin composition may be used in many of the layers, which has a high coefficient of thermal expansion (CTE) (generally about 18 to 100 ppm/° C. in the longitudinal and lateral directions), and a copper (Cu) layer having a coefficient of thermal expansion of about 17 ppm/° C. may be included in each layer. On the outermost layers, solder resist layers may be formed which also have a high rate of thermal expansion (generally about 50 to 150 ppm/° C.). Consequently, the overall coefficient of thermal expansion in the longitudinal and lateral directions for the multi-layer printed circuit board may be about 13 to 30 ppm/° C.
Even in cases where a multi-layer printed circuit board is formed with a resin having high thermal resistance used for the thermosetting resin impregnated into the glass fiber woven fabric, or where an inorganic filler is added to the resin, or a glass fiber woven fabric having a low coefficient of thermal expansion is used as the reinforcement material, the overall coefficient of thermal expansion of the printed circuit board may remain at about 10 to 20 ppm/° C.
The coefficient of thermal expansion of a multi-layer printed circuit board fabricated as above may be much greater than the coefficient of thermal expansion of the semiconductor chip, which is generally about 2 to 3 ppm/° C. With current environmental problems urging the use of lead-free solder in flip chip bonding, this difference can lead to defects reliability tests such as temperature cycle tests, etc. That is, the multi-layer printed circuit board may expand and contract as heat is applied during reliability tests, and the solder and semiconductor chip may be pulled by the expansion and contraction in the longitudinal and lateral directions. As a result, defects may be incurred, such as cracking and delamination in the lead-free solder and damage in the semiconductor chip, etc.
Moreover, in a semiconductor plastic package that has semiconductor chips mounted on one side, the large difference in coefficients of thermal expansion between the semiconductor chips and the multi-layer printed circuit board can lead to significant bending or warpage during the reflowing process.
In an effort to alleviate the stresses when a semiconductor chip is mounted on the multi-layer printed circuit board, a method has been proposed (e.g. Japanese Patent Publication No. 2001-274556) of forming organic insulation layers that have a low coefficient of thermal expansion in the outermost layers of the multi-layer printed circuit board, which has a coefficient of thermal expansion of about 13 to 20 ppm/° C. This publication specifically discloses a multi-layer printed circuit board that uses for the thermally alleviating organic insulation layer a prepreg made by impregnating a thermosetting resin into a reinforcement material of aramid fiber woven fabric, which has a coefficient of thermal expansion of about 9 ppm/° C.
The publication, however, does not provide detailed reliability test results. Also, when a thermally alleviating organic insulation sheet, of 6 to 12 ppm/° C., is used for manufacturing a printed circuit board, the high coefficient of thermal expansion of the inner core printed circuit board may lead to the thermally alleviating organic insulation sheet being pulled and stretched, resulting in the overall coefficient of thermal expansion of the integrated multi-layer printed circuit board exceeding 10 ppm/° C.
When a reliability test, such as a temperature cycle test, etc., is performed for a multi-layer printed circuit board manufactured as above with semiconductor chips mounted using lead-free solder, it may be shown that the organic insulation sheet intended to serve as a thermal buffer may be largely ineffective, because the difference in the rate of thermal expansion between the semiconductor chips and the integrated multi-layer printed circuit boards may cause defects such as cracking and delamination in the lead-free solder connecting the semiconductor chips.
There is also a printed circuit board that uses a metal plate core made of invar or copper-invar, where a B-stage thermosetting resin composition, such as epoxy resin, etc., may be stacked over the metal plate.
In this type of printed circuit board, the difference in coefficients of thermal expansion between the stacked resin layer and the low CTE metal plate core may be extremely large. Thus, when a stress is applied to the printed circuit board, such as during the cutting of the printed circuit board, the resin layer may be delaminated from the metal core, and the reliability of the printed circuit board may be degraded.
Also, as semiconductor chips are mounted on a printed circuit board in higher densities, defects may be incurred by the heat generated by the semiconductor chips.